The present invention relates to a monolithic semi-custom large scale integration (LSI) and, more particularly, to a one-chip LSI suitable for a data processing system. LSI design techniques, including gate array design, have been simplified. Standard cell design has also been simplified recently. A standard cell system of this type is described in "Gate Array and Standard Cell Design Methods", "VLSI DESIGN", June 1984, pp. 79-84. According to this standard cell system, standard cell patterns are prepared in units of function such as registers in order to design and manufacture LSIs. A designer combines and selects circuit patterns to achieve a single target function. However, no contingency is made for a high-packing density design technique of VLSIs, such as is the main feature of the present invention.
In the state-of-the-art gate array and standard cell techniques, it is difficult to pack LSIs such as a microprocessor and its peripheral family chips. Only miscellaneous circuits excluding a microprocessor and its peripheral family chips can be packed at best. Therefore, the most advanced compact hardware logic circuit currently available is constituted by a separate microprocessor, its peripheral family chips and a gate array (or standard cells).
This problem is exemplified by a personal computer system shown in FIG. 1.
The system shown in FIG. 1 has a microprocessor 10 (e.g., Model 8088 available from Intel Corp., U.S.A.), a crystal oscillator 11, a clock generator 12 (e.g., Model 8284A available from Intel Corp.), a bus controller 13 (e.g., Model 8288 available from Intel Corp.), a programmable interrupt controller 14 (e.g., Model 8259A available from Intel Corp.), a programmable DMA controller 15 (e.g., Model 8237A-5 available from Intel Corp.), a programmable interval timer 16 (e.g., Model 8253A-5 available from Intel Corp.), an I/O port 17 (e.g., Model 8255A-5 available from Intel Corp), a CRT controller or CRTC 18 (e.g., Model 46505S available from Hitachi, Ltd., Japan) and a floppy disk controller or FDC 19 (e.g., Model .mu.PD765 available from NEC CORP, Japan).
Furthermore, the system shown in FIG. 1 has an I/O chip selector 20, a random access memory (RAM) 21, an address decoder 22 for the RAM 21, a read only memory (ROM) 23, a ROM decoder 24, an I/O port decoder 25, a timing & decoding circuit 26, a parity check circuit 27, a DMA page register 28, and various buffer registers 29 through 36. The registers 29 and 36 comprise 74LS373s available from Texas Instruments, Inc. (TI), U.S.A. The register 31 comprises a 74LS745 available from TI. The buffer registers 32 and 35 comprise 74LS244s available from TI. The registers 33 and 34 comprise 74LS245s available from TI.
In the system (FIG. 1) arranged as described above, the circuits which can be mounted by conventional gate array and standard cell techniques are a glue circuit, such as the registers 29 through 36. LSIs such as the microprocessor peripheral family chips, and much less the microprocessor 10, the generator 12 and the controller 13, cannot be mounted in the gate array or standard cell.
In order to achieve a higher density, a large scale hardware logic circuit, including a microprocessor and its peripheral family circuits, is proposed, using standard cells or the like to obtain a one-chip LSI. However, when the large scale logic circuit is redesigned, the design work is overloaded, resulting in high development cost and a failure to provide a practical LSI.